1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems incorporating processing pipeline circuitry comprising a plurality of pipeline stages with signal value storage circuits interposed therebetween and incorporating error detection mechanisms.
2. Description of the Prior Art
It is known from WO 2004/084072 to provide data processing systems incorporating processor pipelines that detect errors due to the late arrival of signal transitions at the signal value storage circuits interposed between the processing pipelines. The late arrival of a signal transition at the output of a pipeline stage can give rise to a processing error from which a recovery operation is triggered.
FIG. 1 of the accompanying drawings schematically illustrates processing pipeline circuitry 2 comprising a plurality of pipeline stages 4, 6, 8 with respective signal value storage circuits 10, 12, 14 interposed therebetween. Timing detection circuitry 16, 18, 20 serves to detect signal transitions arriving outside of a nominal timing window at respective signal value storage circuits 10, 12, 14. If a timing violation is detected, then this gives rise to an error signal which is stored within an error latch 22, 24, 26. The error signal E is accumulated as it passes between the pipeline stages by the action of the OR gates 28, 30.
At the output end of the pipeline processing circuitry 2 there are provided two additional pipeline stages with associated signal value storage circuits 32, 34. These additional pipeline stages serve the function of synchronising and stabilising any error signal generated due to a timing violation within the pipeline processing circuitry 2. It will be appreciated that the timing detection circuitry 16, 18, 20 generate an error indicating signal. The error signal is nominally synchronous, but in the event of a near timing violation metastability can occur, and this can cause the error signal to fall at a time which is not synchronised to the next clock edge. As such the error signal is typically considered as an asynchronous signal, and is passed through two synchronising pipeline line stages 32, 34 to reduce the probability of metastability propagating into the error correction logic which is not speculative at the end of the pipeline. This increases the latency associated with obtaining an error signal from the pipeline processing circuitry 2 indicating whether or not a timing violation occurred within the processing pipeline circuitry 2.
FIG. 2 of the accompanying drawings is a signal diagram schematically illustrating the operation of the processing pipeline circuitry 2 of FIG. 2. A clock signal CK serves to control and regulate the processing performed by the processing pipeline circuitry 2. Signal values are captured into the signal value storage circuitry 10, 12, 14, 32, 34 at the rising edge of the clock signal CK. A nominal timing window corresponding to the period preceding the setup time before the rising edge of the clock signal CK and corresponds to the period within which during normal operation one would expect a signal transition to arrive at a signal value storage circuit 10, 12, 14, 32, 34. If a signal transition occurs outside of this nominal timing window, then it corresponds to a timing violation and an error signal is generated. The signals D2 [31:0] correspond to the signal values input to the signal value storage circuitry 14 of FIG. 1. In the example of FIG. 2, one or more signal transitions within the signals D2 [31:0] arrive late and are outside the nominal timing window. The timing detection circuitry 20 detects this late arriving signal transition and asserts an error signal which is stored into the latch 26 at the next rising edge of the clock signal CK. This error signal is then passed along to the latch 38 associated with the final pipeline stage and is output from the pipeline processing circuitry 2 to indicate that a timing error has occurred within the pipeline processing circuitry 2.